un.aarch64

QNX SDP8.0Building Embedded SystemsConfigurationDeveloper

System page information specific to AArch64

Usually, startup library functions automatically fill in this structure, which contains the following members:
L0_vaddr
Virtual address of the MMU level-zero page table used to map the kernel.
gic_map
Variable-sized map of CPU numbers to values for sending IPIs.

For a given CPU number, the corresponding map entry stores a value needed to send an IPI to that particular CPU. It can be simply the CPU number according to the GIC (which can be different than the CPU number according to procnto), or even a full affinity value identifying the CPU as needed by the GICv3 system register interface.

gicr_map
Variable-sized map of CPU numbers to GIC redistributor array indexes.

For a given CPU number, the corresponding map entry stores the index of the redistributor array for the same CPU. This is needed for the GICv3 PPI callouts and for VMs in a hypervisor system to look at the right redistributor index regardless of the procnto view of CPU ordering.

In each 32-bit map entry, the top 16 bits indicate the redistributor range (if there are several discontiguous ranges), and the bottom 16 bits indicate the index into that range.

idreg_dump
AArch64 ID register space. This variable-sized array has 56 entries per CPU that store the values of the identification registers between S3_0_C0_C1_0 and S3_0_C0_C7_7. For more information, refer to the ARM Architecture Reference Manual and your target's hardware manual.
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