cpuinfo

The cpuinfo area contains information about each CPU in the system, such as the CPU type, speed, capabilities, performance, and cache sizes.

The number of cpuinfo_entry instances is equal to the value in the num_cpu member of the syspage_entry structure. Each cpuinfo_entry structure is automatically filled in by the startup library function init_cpuinfo(). The members include:

cpu

A number that represents the type of CPU. The meaning of this number depends on the CPU architecture. For example, for the x86 processor family, this number is the processor chip number (e.g., 586).

speed

The MHz rating of the processor.

flags

The CPU capabilities; see flags below.

smp_hwcoreid

A number identifying each core; used for SMP.

idle_history

Reserved.

spare1

Not used.

name

An index into the strings member in the system page structure. The character string at the specified index contains an ASCII, NULL-terminated machine name.

ins_cache

An index into the cacheattr array, which is described below. This index points to the first definition in a list for the instruction cache.

data_cache

An index into the cacheattr array, which is described below. This index points to the first definition in a list for the data cache.

flags

The flags member contains a bitmapped indication of the CPU's capabilities. The prefix for a flag name (i.e., macro constant) indicates the CPU family it applies to. For instance, AARCH64_ indicates this constant is for use on the AArch64 (64-bit ARM) family of processors. If there is no prefix, the constant is generic; it is relevant to any CPU supported by QNX OS.

Generic flags are defined in <sys/syspage.h>, while architecture-specific flags are defined in <arch/syspage.h>. You'll need the values to interpret the output of the pidin syspage command.

LL/SC vs LSE atomic operations

The ARMv8-A architecture (see https://developer.arm.com/documentation/ddi0487/latest/) provides two groups of opcodes for atomic operations:

• standard load-link/store conditional (LLSC)
• ARMv8.1-A Large System Extension (LSE)

On the 64-bit ARM variant of procnto, if all CPUs support LSE atomics, the set of QNX-specific atomic functions default to using LSE, otherwise we revert to LLSC. The following QNX OS functions are affected:

• atomic_add()
• atomic_add_value()
• atomic_clr()
• atomic_clr_value()
• atomic_set()
• atomic_set_value()
• atomic_sub()
• atomic_sub_value()
• atomic_toggle()
• atomic_toggle_value()

Note that pthread_spin_lock() and pthread_spin_trylock() use these atomic functions; pthread_barrier_wait() and pthread_mutex_destroy() also use them, but to a lesser extent.

If all the CPUs in your system support ARMv8.1-A LSE atomics, you can profile these functions using both LLSC and LSE to determine which version gives better performance. On systems that default to LSE, you can revert to using LLSC by clearing the AARCH64_CPU_FLAG_LSE flag in the system page by either temporarily modifying the startup, or if the startup supports the -F option, clearing the CPU flag by passing -F~0x8000 to startup.

Note that the set of C11-specific atomic functions (such as atomic_fetch_add() in stdatomic.h) use LSE instructions only if you specify -march==armv8-a+lse or -march=armv8.N (where N is 1 or higher) on the compiler command line. The default is to build for the lowest common denominator ARMv8 instruction set, which doesn't include the LSE instructions.