Interrupt latency
Interrupt latency is the time between the assertion of the hardware interrupt and the execution of the first instruction after the IST returns from the kernel after blocking to wait for an interrupt.
- Device to PIC - this is hardware bound and out of OS control
- PIC to exception handler - this is affected by the disabling of interrupts on the core to which the interrupt is routed, and the masking of the interrupt source.
- Exception handler to IST - this is affected by scheduling overhead, and scheduling configuration such as priority and prcoessor affinity.
The OS leaves interrupts fully enabled almost all the time, so the effect on interrupt latency is typically insignificant. But certain critical sections of code do require that interrupts be temporarily disabled.
Scheduling latency is the time between the last instruction of the kernel's exception handler and the execution of the first instruction of a driver thread. This usually means the time it takes to save the context of the currently executing thread and restore the context of the required driver thread. This time is also kept small in a QNX OS system.
The interrupt latency (Til) in the above diagram represents the minimum latency—that which occurs when interrupts were fully enabled at the time the interrupt occurred. Worst-case interrupt latency will be this time plus the longest time in which the OS, or the running system process, disables CPU interrupts.