Processing interrupts

QNX SDP8.0Getting Started with the QNX OSDeveloperUser

Interrupt processing requires three hardware components; the device that generates the interrupt (e.g., a timer, serial device, network card, graphics processor, etc.), a processor, and an interrupt controller (connected to both the device and the processor). Typically, devices deliver device-specific interrupts to an interrupt controller, which then delivers the interrupts to a processor. This allows the software to recognize which device sent the interrupt and assign a relevant device driver (software that manages a specific device) to handle it. With a multi-processor system, you can configure the interrupt controller to deliver specific interrupts to a specific processor, or to a subset of the processors depending on the controller.

The kernel represents the software that enables the processor to switch from running the normal instruction stream to servicing an interrupt. In a microkernel system, such as QNX, the device driver is typically a stand-alone user process, where the driver isn't part of the kernel.

When a device generates an interrupt and the interrupt controller notices it, the controller notifies the processor. If the processor has interrupts enabled, it immediately jumps to a pre-defined code address, where it expects to find the kernel code for handling interrupts. The kernel stores the processor registers so that the thread can resume its processing after the interrupt has passed. The kernel queries the interrupt controller to determine the interrupt source and notifies the device driver to take action.

Once the device driver has processed the interrupt, it notifies the interrupt controller so that the controller can prepare to receive the next interrupt event. The kernel then blocks the interrupt, from the time the processor jumps to the kernel's entry routine to when the device driver finishes handling it, to prevent an infinite sequence of jumps to the entry routine. This blocking can either occur at the processor level, which blocks all interrupts to that processor, or at the controller level, which allows for the masking of a specific interrupt.

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