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SSE usage with QNX

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Applicable Environment

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Topic: SSE usage with QNX
SDP: 6.5.0
Target: Any supported target

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Recommendation

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Q: I would like to know if it is possible/safe to use SSE instructions with QNX. I.e., does the kernel correctly save/restore SSE registers/state during context switches?

A: Yes, it saves/restores the context.

Q: And is there any API or structures/constants to check availability/level of SSE rather than examining processor features directly via inline assembler?

A:Check the CPU flags of in the SYSPAGE_ENTRY(cpuinfo)->flags for :

X86_CPU_MMX, X86_CPU_SIMD, X86_CPU_SSE2 . SSE3 is not enumerated and will required inline assembly to probe.

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NOTE: This entry has been validated against the SDP version listed above. Use caution when considering this advice for any other SDP version. For supported releases, please reach out to QNX Technical Support if you have any questions/concerns.

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