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Applicable Environment
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- Topic: msr - read/write x86 CPU MSRs
- SDP: 6.5.0 SP1
- Target: x86 targets
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Recommendation
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msr [ number [ new_value ] ]
If no <number> is given, the TSC is read.
If no <new_value> is provided, the MSR is only read.
If both <number> and <new_value> are given, the MSR is read and set.
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What happens?
MSRs (aside from the TSC) are only accessible in RING0, i.e., in
kernel space. Regular processes, even with I/O privileges, will
get you no further than RING1.
So to access MSRs, you need to operate in a kernel context - but
how to get there?
One -rather obvious- way is to attach an interrupt handler.
Since it is called from within the kernel, it will have the required
privileges and can perform the necessary operations for us.
*/
See attachment msr.c
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NOTE:
This entry has been validated against the SDP version listed above. Use
caution when considering this advice for any other SDP version. For
supported releases, please reach out to QNX Technical Support if you have any questions/concerns. ________________________________________________________________________
