Interrupts & controllers

On an x86 design, the default startup supports two Programmable Interrupt Controllers (PICs). These must be 8259-compatible, with the standard configuration of a secondary 8259 connected to the IRQ2 line of the primary interrupt controller.

Note: Beware of hanging devices off IRQ7 and IRQ15 on an 8259 chip — these are generally known as the "glitch interrupts" and can be unreliable.

If your x86 hardware design differs, there's no constraint about the PICs, but you must write the code to handle them.

On non-x86 designs, be aware that there may be only one interrupt line going to the processor and that a number of hardware devices may be sharing that one line. This is generally accomplished in one of two ways:

In either case, the relevant design issue is to determine the ordering and priority of interrupts from hardware sources. You'll want to arrange the hardware and software to give highest priority (and first order) to the interrupt source that has the most stringent latency requirements. (For more details, see the chapter on Writing an Interrupt Handler in the Programmer's Guide, along with the InterruptAttach() and InterruptAttachEvent() function calls in the QNX Neutrino C Library Reference.)