The cpuinfo area contains information about each CPU chip in the system, such as the CPU type, speed, capabilities, performance, and cache sizes. There are as many elements in the cpuinfo structure as the num_cpu member indicates (e.g. on a dual-processor system, there will be two cpuinfo entries).

This table is filled automatically by the library function init_cpuinfo().

Member Description
cpu This is a number that represents the type of CPU. Note that this number will vary with the CPU architecture. For example, on the x86 processor family, this number will be the processor chip number (e.g. 486, 586).
speed Contains the MHz rating of the processor.
flags See below.
name Contains an index into the strings member in the system page structure. The character string at the specified index contains an ASCII, NULL-terminated machine name.
ins_cache Contains an index into the cacheattr array, described below. This index points to the first definition in a list for the instruction cache.
data_cache Contains an index into the cacheattr array, described below. This index points to the first definition in a list for the data cache.

The flags member contains a bitmapped indication of the capabilities of the CPU chip. Note that the prefix for the manifest constant indicates which CPU family it applies to (e.g. ARM_ indicates this constant is for use by the ARM family of processors). In the case of no prefix, it indicates that it's generic to any CPU.

The bits include the following:

This bit: Means that the CPU has or supports:
CPU_FLAG_FPU A Floating Point Unit (FPU)
CPU_FLAG_MMU A Memory Management Unit (MMU), and the MMU is enabled (i.e., the CPU is currently in virtual addressing mode)
ARM_CPU_FLAG_CC_INCR_BIT_32 A 32-bit clock cycle counter (CLOCKCYCLES_INCR_BIT is 32)
ARM_CPU_FLAG_IDIV H/W division: the UDIV and SDIV instructions are supported
ARM_CPU_FLAG_NEON NEON technology, a 128-bit SIMD (Single Instruction, Multiple Data) architecture extension to the ARM Cortex-A series processor
ARM_CPU_FLAG_SMP Multiple processors
ARM_CPU_FLAG_V7 ARMv7 architecture
ARM_CPU_FLAG_V7_MP ARMv7 multiprocessor extensions
ARM_CPU_FLAG_WMMX2 An iWMMX2 coprocessor
X86_CPU_AVX Advanced Vector Extensions
X86_CPU_BSWAP BSWAP instruction
X86_CPU_CMOV CMOVxx instructions
X86_CPU_CPUID CPUID instruction
X86_CPU_INVLPG INVLPG instruction
X86_CPU_MMX MMX instructions
X86_CPU_MTRR MTRR (Memory Type Range Register) registers
X86_CPU_NX No-eXecute PTE bit
X86_CPU_PAE Extended addressing
X86_CPU_PAT Page Attribute Tables
X86_CPU_PGE TLB (Translation Lookaside Buffer) global mappings
X86_CPU_PSE Page size extensions
X86_CPU_PTESPLIT_TLBFLUSH Needs TLB flush when splitting a large page
X86_CPU_RDTSC RDTSC instruction
X86_CPU_SEP SYSENTER and SYSEXIT instructions
X86_CPU_SIMD SIMD instructions
X86_CPU_SSE2 Streaming SIMD Extensions 2
X86_CPU_XSAVE XSAVE and XRSTOR instructions
X86_CPU_WP WP bit in the CR0 register