Capability ID 0x10 (PCI Express)

Updated: May 06, 2022

The PCIe capability module provides access to the extended configuration space from 256–4095 bytes using the following APIs, which are defined in <pci/cap_pcie.h>:

int_t cap_pcie_version( pci_cap_t cap )
Return the version of PCI Express supported by the device or -1 on any error.
pci_err_t cap_pcie_read_portType( pci_cap_t cap, cap_pcie_portType_t *portType )
If PCI_ERR_OK is returned, portType contains the PCIe port type for the device.
bool_t cap_pcie_is_slot_implemented(pci_cap_t cap )
Returns true or false, depending on whether the Root Port supports slots.
int_t cap_pcie_read_slot_num(pci_cap_t cap )
Returns the assigned slot number if the Root Port supports slots, or -1 on error.
int_t cap_pcie_read_int_msgnum(pci_cap_t cap )
Returns the MSI interrupt number used for PCIe status register changes.

The PCIe extended capability functions (analogous to their PCI library counterparts) include:

pci_err_t cap_pcie_read_xtnd_capid(pci_cap_t cap, pcie_capid_t *capid, uint_t idx )
Analogous to pci_device_read_capid().
int_t cap_pcie_find_xtnd_capid(pci_cap_t cap, pcie_capid_t capid )
Analogous to pci_device_find_capid().
int_t cap_pcie_read_xtnd_capid_version(pcie_cap_t xtnd_cap, pcie_capid_t capid )
Returns the extended capability version, or -1 on error.
pci_err_t cap_pcie_read_xtnd_cap(pci_cap_t cap, pcie_cap_t *xtnd_cap, uint_t idx )
Analogous to pci_device_read_cap().

The following APIs access the PCIe device capability, control, and status registers at offsets 0x4/0x24, 0x8/0x28 and 0xA/0x2A, respectively. For all successful writes, the parameter that contains the value to be written is updated with the current register contents after the write is completed:

pci_err_t cap_pcie_read_dev_cap_reg( pci_cap_t cap, cap_pcie_cap_reg_t *dev_cap_reg )
pci_err_t cap_pcie_read_dev_cap_reg2( pci_cap_t cap, cap_pcie_cap_reg_t *dev_cap_reg )
pci_err_t cap_pcie_read_dev_ctrl_reg( pci_cap_t cap, cap_pcie_ctrl_reg_t *dev_ctrl_reg )
pci_err_t cap_pcie_read_dev_ctrl_reg2( pci_cap_t cap, cap_pcie_ctrl_reg_t *dev_ctrl_reg )
pci_err_t cap_pcie_read_dev_stat_reg( pci_cap_t cap, cap_pcie_stat_reg_t *dev_stat_reg )
pci_err_t cap_pcie_read_dev_stat_reg2( pci_cap_t cap, cap_pcie_stat_reg_t *dev_stat_reg )
pci_err_t cap_pcie_write_dev_ctrl_reg( pci_devhdl_t hdl, pci_cap_t cap,
                                       cap_pcie_ctrl_reg_t *dev_ctrl_reg )
pci_err_t cap_pcie_write_dev_ctrl_reg2( pci_devhdl_t hdl, pci_cap_t cap,
                                        cap_pcie_ctrl_reg_t *dev_ctrl_reg )
pci_err_t cap_pcie_write_dev_stat_reg( pci_devhdl_t hdl, pci_cap_t cap,
                                       cap_pcie_stat_reg_t *dev_stat_reg )
pci_err_t cap_pcie_write_dev_stat_reg2( pci_devhdl_t hdl, pci_cap_t cap,
                                        cap_pcie_stat_reg_t *dev_stat_reg )

The following APIs access the PCIe link capabilities, control, and status registers at offsets 0xC/0x2C, 0x10/0x30 and 0x12/0x32, respectively. For all successful writes, the parameter that contains the value to be written is updated with the current register contents after the write is completed:

pci_err_t cap_pcie_read_link_cap_reg( pci_cap_t cap, cap_pcie_cap_reg_t *link_cap_reg )
pci_err_t cap_pcie_read_link_cap_reg2( pci_cap_t cap, cap_pcie_cap_reg_t *link_cap_reg )
pci_err_t cap_pcie_read_link_ctrl_reg( pci_cap_t cap, cap_pcie_ctrl_reg_t *link_ctrl_reg )
pci_err_t cap_pcie_read_link_ctrl_reg2( pci_cap_t cap, cap_pcie_ctrl_reg_t *link_ctrl_reg )
pci_err_t cap_pcie_read_link_stat_reg( pci_cap_t cap, cap_pcie_stat_reg_t *link_stat_reg )
pci_err_t cap_pcie_read_link_stat_reg2( pci_cap_t cap, cap_pcie_stat_reg_t *link_stat_reg )
pci_err_t cap_pcie_write_link_ctrl_reg( pci_devhdl_t hdl, pci_cap_t cap,
                                        cap_pcie_ctrl_reg_t *link_ctrl_reg )
pci_err_t cap_pcie_write_link_ctrl_reg2( pci_devhdl_t hdl, pci_cap_t cap,
                                         cap_pcie_ctrl_reg_t *link_ctrl_reg )
pci_err_t cap_pcie_write_link_stat_reg( pci_devhdl_t hdl, pci_cap_t cap,
                                        cap_pcie_stat_reg_t *link_stat_reg )
pci_err_t cap_pcie_write_link_stat_reg2( pci_devhdl_t hdl, pci_cap_t cap,
                                         cap_pcie_stat_reg_t *link_stat_reg )

The following APIs access the PCIe slot capabilities, control, and status registers at offsets 0x14/0x34, 0x18/0x38 and 0x1A/0x3A, respectively. For all successful writes, the parameter that contains the value to be written is updated with the current register contents after the write is completed:

pci_err_t cap_pcie_read_slot_cap_reg( pci_cap_t cap, cap_pcie_cap_reg_t *slot_cap_reg )
pci_err_t cap_pcie_read_slot_cap_reg2( pci_cap_t cap, cap_pcie_cap_reg_t *slot_cap_reg )
pci_err_t cap_pcie_read_slot_ctrl_reg( pci_cap_t cap, cap_pcie_ctrl_reg_t *slot_ctrl_reg )
pci_err_t cap_pcie_read_slot_ctrl_reg2( pci_cap_t cap, cap_pcie_ctrl_reg_t *slot_ctrl_reg )
pci_err_t cap_pcie_read_slot_stat_reg( pci_cap_t cap, cap_pcie_stat_reg_t *slot_stat_reg )
pci_err_t cap_pcie_read_slot_stat_reg2( pci_cap_t cap, cap_pcie_stat_reg_t *slot_stat_reg )
pci_err_t cap_pcie_write_slot_ctrl_reg( pci_devhdl_t hdl, pci_cap_t cap,
                                        cap_pcie_ctrl_reg_t *slot_ctrl_reg )
pci_err_t cap_pcie_write_slot_ctrl_reg2( pci_devhdl_t hdl, pci_cap_t cap,
                                         cap_pcie_ctrl_reg_t *slot_ctrl_reg )
pci_err_t cap_pcie_write_slot_stat_reg( pci_devhdl_t hdl, pci_cap_t cap,
                                        cap_pcie_stat_reg_t *slot_stat_reg )
pci_err_t cap_pcie_write_slot_stat_reg2( pci_devhdl_t hdl, pci_cap_t cap,
                                         cap_pcie_stat_reg_t *slot_stat_reg )

The following APIs access the PCIe root capabilities, control, and status registers at offsets 0x1C, 0x1E and 0x20 respectively. For all successful writes, the parameter that contains the value to be written is updated with the current register contents after the write is completed:

pci_err_t cap_pcie_read_root_cap_reg( pci_cap_t cap, cap_pcie_root_cap_reg_t *root_cap_reg )
pci_err_t cap_pcie_read_root_ctrl_reg( pci_cap_t cap, cap_pcie_root_ctrl_reg_t *root_ctrl_reg )
pci_err_t cap_pcie_read_root_stat_reg( pci_cap_t cap, cap_pcie_root_stat_reg_t *root_stat_reg )
pci_err_t cap_pcie_write_root_ctrl_reg( pci_devhdl_t hdl, pci_cap_t cap,
                                        cap_pcie_root_ctrl_reg_t *root_ctrl_reg )
pci_err_t cap_pcie_write_root_stat_reg( pci_devhdl_t hdl, pci_cap_t cap,
                                        cap_pcie_root_stat_reg_t *root_stat_reg )