_pci_config

PCI configuration registers

Synopsis:

#include <qvm/hw_pci.h>

struct _pci_config_regs {
    uint16_t Vendor_ID;
    uint16_t Device_ID;
    uint16_t Command;
    uint16_t Status;
    uint8_t Revision_ID;
    uint8_t Class_Code[3];
    uint8_t Cache_Line_Size;
    uint8_t Latency_Timer;
    uint8_t Header_Type;
    uint8_t BIST;
    uint32_t Base_Address_Regs[6];
    uint32_t Cardbus_CIS;
    uint16_t Sub_Vendor_ID;
    uint16_t Sub_System_ID;
    uint32_t ROM_Base_Address;
    uint8_t Capabilities_Pointer;
    uint8_t Reserved2[3];
    uint32_t Reserved3;
    uint8_t Interrupt_Line;
    uint8_t Interrupt_Pin;
    uint8_t Min_Gnt;
    uint8_t Max_Lat;
    uint8_t Device_Dependent_Regs[192];
} ;

Data:

uint16_t Vendor_ID: 0x00
uint16_t Device_ID: 0x02
uint16_t Command: 0x04
uint16_t Status: 0x06
uint8_t Revision_ID: 0x08
uint8_t Class_Code[3]: 0x09
uint8_t Cache_Line_Size: 0x0C
uint8_t Latency_Timer: 0x0D
uint8_t Header_Type: 0x0E
uint8_t BIST: 0x0F
uint32_t Base_Address_Regs[6]: 0x10
uint32_t Cardbus_CIS: 0x28
uint16_t Sub_Vendor_ID: 0x2C
uint16_t Sub_System_ID: 0x2E
uint32_t ROM_Base_Address: 0x30
uint8_t Capabilities_Pointer: 0x34
uint8_t Reserved2[3]: 0x35
uint32_t Reserved3: 0x38
uint8_t Interrupt_Line: 0x3C
uint8_t Interrupt_Pin: 0x3D
uint8_t Min_Gnt: 0x3E
uint8_t Max_Lat: 0x3F
uint8_t Device_Dependent_Regs[192]: Device-dependent registers

Library:

Provided by qvm; no external library is required.

Description:

See the PCI specification.