(QNX Neutrino 6.5.0 or later)
struct armv_cache {
const struct arm_cache_config *dcache_config;
const struct callout_rtn *dcache_rtn;
const struct arm_cache_config *icache_config;
const struct callout_rtn *icache_rtn;
};
The armv_cache structure describes the CPU caches. The members include:
- dcache_config
- Describes the data cache. It's required only when a CPU doesn't implement the CP15 cache-type register.
When a CPU does implement the CP15 cache-type register, set this to 0, so that the startup library will use
arm_add_cache() to determine the cache register configuration based on the CP15 cache-type register.
- dcache_rtn
- Manage the data cache with the help of a callout.
- icache_config
- Describes the instruction cache.
This is required only if the CPU doesn't implement the CP15 cache
type register.
When a CPU does implement the CP15 cache-type register, set this to 0, so that the startup library will use
arm_add_cache() to determine the cache register configuration based on the CP15 cache-type register.
- icache_rtn
- Manage the instruction cache with the help of a callout.