The cpuinfo area contains information about each CPU chip in the system, such as the CPU type, speed, capabilities, performance, and cache sizes. There are as many elements in the cpuinfo structure as the num_cpu member indicates (e.g. on a dual-processor system, there will be two cpuinfo entries).
This table is filled automatically by the library function init_cpuinfo().
| Member | Description |
|---|---|
| cpu | This is a number that represents the type of CPU. Note that this number will vary with the CPU architecture. For example, on the x86 processor family, this number will be the processor chip number (e.g. 486, 586). On MIPS and PowerPC, this is filled with the contents of the version registers. |
| speed | Contains the MHz rating of the processor. For example, on a 300 MHz MIPS R4000, this number would be 300. |
| flags | See below. |
| name | Contains an index into the strings member in the system page structure. The character string at the specified index contains an ASCII, NULL-terminated machine name (e.g. on a MIPS R4000 it will be the string "R4000"). |
| ins_cache | Contains an index into the cacheattr array, described below. This index points to the first definition in a list for the instruction cache. |
| data_cache | Contains an index into the cacheattr array, described below. This index points to the first definition in a list for the data cache. |
The flags member contains a bitmapped indication of the capabilities of the CPU chip. Note that the prefix for the manifest constant indicates which CPU family it applies to (e.g. PPC_ indicates this constant is for use by the PowerPC family of processors). In the case of no prefix, it indicates that it's generic to any CPU.
Here are the constants and their defined meanings:
| This constant: | Means that the CPU has or supports: |
|---|---|
| CPU_FLAG_FPU | Floating Point Unit (FPU). |
| CPU_FLAG_MMU | Memory Management Unit (MMU), and the MMU is enabled (i.e. the CPU is currently in virtual addressing mode). |
| X86_CPU_CPUID | CPUID instruction. |
| X86_CPU_RDTSC | RDTSC instruction. |
| X86_CPU_INVLPG | INVLPG instruction. |
| X86_CPU_WP | WP bit in the CR0 register. |
| X86_CPU_BSWAP | BSWAP instruction. |
| X86_CPU_MMX | MMX instructions. |
| X86_CPU_CMOV | CMOVxx instructions. |
| X86_CPU_PSE | Page size extensions. |
| X86_CPU_PGE | TLB (Translation Lookaside Buffer) global mappings. |
| X86_CPU_MTRR | MTRR (Memory Type Range Register) registers. |
| X86_CPU_SEP | SYSENTER/SYSEXIT instructions. |
| X86_CPU_SIMD | SIMD instructions. |
| X86_CPU_FXSR | FXSAVE/FXRSTOR instructions. |
| X86_CPU_PAE | Extended addressing. |
| PPC_CPU_EAR | EAR (External Address Register) register. |
| PPC_CPU_HW_HT | Hardware hash table. |
| PPC_CPU_HW_POW | Power management. |
| PPC_CPU_FPREGS | Floating point registers. |
| PPC_CPU_SW_HT | Software hash table. |
| PPC_CPU_ALTIVEC | AltiVec extensions. |
| PPC_CPU_XAEN | Extended addressing. |
| PPC_CPU_XASPACE | Power ISA 2.06 External Process ID Registers, which the kernel uses to optimize the passing of messages between different address spaces. As the Freescale e500mc is currently the only PPC to implement these features, it's the only processor for which you should set this flag. Setting it on other processors will have unpredictable results. |
| PPC_CPU_SW_TLBSYNC | Sync TLBs. |
| PPC_CPU_TLB_SHADOW | Shadow registers in TLB handler. |
| PPC_CPU_DCBZ_NONCOHERENT | DCBZ problems. |
| PPC_CPU_STWCX_BUG | Requires a workaround to avoid a hardware problem with an unpaired stwcx. instruction when the kernel switches contexts. |
| MIPS_CPU_FLAG_PFNTOPSHIFT_MASK | Construct TLB entries. |
| MIPS_CPU_FLAG_MAX_PGSIZE_MASK | Maximum number of masks. |
| MIPS_CPU_FLAGS_MAX_PGSIZE_SHIFT | Maximum number of shifts. |
| MIPS_CPU_FLAG_L2_PAGE_CACHE_OPS | L2 cache. |
| MIPS_CPU_FLAG_64BIT | 64-bit registers. |
| MIPS_CPU_FLAG_128BIT | 128-bit registers. |
| MIPS_CPU_FLAG_SUPERVISOR | Supervisor mode. |
| MIPS_CPU_FLAG_NO_WIRED | No wired register. |
| MIPS_CPU_FLAG_NO_COUNT | No count register. |