The interpretation of the cpu_intr_base member varies with the processor:
| Processor | Interpretation |
|---|---|
| x86 | The IDT (Interrupt Descriptor Table) entry, typically 0x30. |
| PPC | The offset from the beginning of the exception table where execution begins when an external interrupt occurs. A sample value is 0x0140, calculated by 0x0500 / 4. |
| PPC/BE | Interrupts no longer start at fixed locations in low memory. Instead there's a set of IVOR (Interrupt Vector Offset Register) registers. Each exception class has a different IVOR. When you specify the interrupt layout to startup, you'll need to identify the particular IVOR register the processor will use when the interrupt occurs. For example, PPCBKE_SPR_IVOR4 is used for normal external interrupts; PPCBKE_SPR_IVOR10 is used for decrementer interrupts. See startup/boards/440rb/init_intrinfo.c for an example of what to do on bookE CPUs. |
| PPC/Non-BE | — |
| MIPS | The value in the "cause" register when an external interrupt occurs. A sample value is 0. |
| ARM | This value should be 0, since all ARM interrupts are handled via the IRQ exception. |
| SH | The offset from the beginning of the exception table where execution starts when an interrupt occurs. For example, for 7750, the value is 0x600. |