Do:

• Do design in more speed/memory than you think you need.
• Do try a proof of concept using off-the-shelf hardware, if possible.
• Do have a serial port/debug output device on the board; have it reasonably close to the CPU in hardware terms (i.e. don't put it on the other side of a PCI bridge).
• Do allow the ROM/flash devices holding the IPL code to be socketed.
• If you're using a MIPS processor, make sure any devices needed by the IPL/startup sequence are in the physical address range of 0x00000000 to 0x20000000 — that makes it accessible from the kseg1 virtual address block.
• Do consider staggering a device's ports by any power of 2, but don't mix up the address lines so that the I/O registers appear in a strange order.
• Do try to use a timer chip that allows free-running operation, rather than one that requires poking after every interrupt.
• Do put the timer on its own interrupt line so that the kernel doesn't have to check that the interrupt actually came from the timer.
• Do follow the CPU's interface for reporting a bus error — don't report it as a hardware interrupt.
• If you have optional pieces, make sure you have some positive method of determining what pieces are present (something other than poking at it and seeing if it responds).
• Do run your design by us, ideally before you build it.
• Do make a point of stating requirements you think are obvious.
• Do remember to point out any pitfalls you know about.
• Do send us as much documentation as you have available on chipsets, panels, etc.