Definitions in vpci.h

#define VPCI_ROM_BAR 0x6u

Reserved memory BAR type to mark the ROM BAR. Bits 1 and 2 cannot be set to one in either I/O or memory BARs.

#define VPCI_SLICE_DESCRIPTOR_COMMAND { \
	.writable = (wr), \
	.offset = (uint16_t)offsetof(struct _pci_config_regs, Command),	\
	.nbytes = 2, \
	.tag = 0, \
	.store_offset = (uint16_t)offsetof(struct vpci_rw_state, command) \
	}

Slice descriptor for a command register.

#define VPCI_SLICE_DESCRIPTOR_STATUS { \
	.writable = (wr), \
	.offset = (uint16_t)offsetof(struct _pci_config_regs, Status), \
	.nbytes = 2, \
	.tag = 0, \
	.store_offset = (uint16_t)offsetof(struct vpci_rw_state, status) \
	}

Slice descriptor for a status register.

#define VPCI_SLICE_DESCRIPTOR_CACHE_LINE_SIZE { \
	.writable = 0xff, \
	.offset = (uint16_t)offsetof(struct _pci_config_regs, Cache_Line_Size), \
	.nbytes = 1, \
	.tag = 0, \
	.store_offset = (uint16_t)offsetof(struct vpci_rw_state, cache_line_size) \
	}

Slice descriptor for a cache line size register.

#define VPCI_SLICE_DESCRIPTOR_LATENCY_TIMER { \
	.writable = 0xff, \
	.offset = (uint16_t)offsetof(struct _pci_config_regs, Latency_Timer), \
	.nbytes = 1, \
	.tag = 0, \
	.store_offset = (uint16_t)offsetof(struct vpci_rw_state, latency_timer) \
	}

Slice descriptor for a latency timer register.

#define VPCI_SLICE_DESCRIPTOR_BAR32 { \
	.writable = (wr), \
	.offset = (uint16_t)offsetof(struct _pci_config_regs, Base_Address_Regs[(idx)]), \
	.nbytes = 4, \
	.tag = 0, \
	.store_offset = (uint16_t)offsetof(struct vpci_rw_state, bars[(idx)].vb_value) \
	}

Slice descriptor for a 32-bit BAR register.

#define VPCI_SLICE_DESCRIPTOR_BAR64 { \
		.writable = (wr), \
		.offset = (uint16_t)offsetof(struct _pci_config_regs, Base_Address_Regs[(idx)]),\
		.nbytes = 4, \
		.tag = 0, \
		.store_offset = (uint16_t)offsetof(struct vpci_rw_state, bars[(idx)].vb_value) \
	}, { \
		.writable = ~0u, \
		.offset = (uint16_t)offsetof(struct _pci_config_regs, Base_Address_Regs[(idx)+1]), \
		.nbytes = 4, \
		.tag = 0, \
		.store_offset = (uint16_t)offsetof(struct vpci_rw_state, bars[(idx)].vb_value_upper) \
	}

Slice descriptor for a 64-bit BAR register.

#define VPCI_SLICE_DESCRIPTOR_INTERRUPT_LINE { \
	.writable = 0xff, \
	.offset = (uint16_t)offsetof(struct _pci_config_regs, Interrupt_Line), \
	.nbytes = 1, \
	.tag = 0, \
	.store_offset = (uint16_t)offsetof(struct vpci_rw_state, interrupt_line) \
	}

Slice descriptor for an interrupt line register.

#define VPCI_SLICE_DESCRIPTOR_INTERRUPT_PIN { \
	.writable = 0xff, \
	.offset = (uint16_t)offsetof(struct _pci_config_regs, Interrupt_Pin), \
	.nbytes = 1, \
	.tag = 0, \
	.store_offset = (uint16_t)offsetof(struct vpci_rw_state, interrupt_pin) \
	}

Slice descriptor for an interrupt pin register.

#define VPCI_SLICE_DESCRIPTOR_ONE_BAR32 VPCI_SLICE_DESCRIPTOR_COMMAND((cmd)), \
	VPCI_SLICE_DESCRIPTOR_STATUS((status)), \
	VPCI_SLICE_DESCRIPTOR_CACHE_LINE_SIZE(), \
	VPCI_SLICE_DESCRIPTOR_LATENCY_TIMER(),\
	VPCI_SLICE_DESCRIPTOR_BAR32(0, (addr_bits)), \
	VPCI_SLICE_DESCRIPTOR_INTERRUPT_LINE(), \
	VPCI_SLICE_DESCRIPTOR_INTERRUPT_PIN() /* <STAN_MACRO1> */

Slice descriptor array for a virtual PCI device with one 32-bit BAR.

#define VPCI_NUM_ONE_BAR32_SLICES 7

The number of descriptor entries in a virtual PCI device with one 32 bit BAR.

#define VPCI_SLICE_DESCRIPTOR_ONE_BAR64 VPCI_SLICE_DESCRIPTOR_COMMAND((cmd)), \
	VPCI_SLICE_DESCRIPTOR_STATUS((status)), \
	VPCI_SLICE_DESCRIPTOR_CACHE_LINE_SIZE(), \
	VPCI_SLICE_DESCRIPTOR_LATENCY_TIMER(), \
	VPCI_SLICE_DESCRIPTOR_BAR64(0, (addr_bits)), \
	VPCI_SLICE_DESCRIPTOR_INTERRUPT_LINE(), \
	VPCI_SLICE_DESCRIPTOR_INTERRUPT_PIN() /* <STAN_MACRO1> */

Slice descriptor array for a virtual PCI device with one 64-bit BAR.

#define VPCI_NUM_ONE_BAR64_SLICES (VPCI_NUM_ONE_BAR32_SLICES + 1)

The number of descriptor entries in a virtual PCI device with one 64-bit BAR.