armv_chip

Synopsis:

struct armv_chip {
        unsigned                  cpuid;
        const char                *name;
        unsigned                  mmu_cr_set;
        unsigned                  mmu_cr_clr;
        int                       cycles;
        const struct armv_cache   *cache;
        const struct callout_rtn  *power;
        const struct callout_rtn  *flush;
        const struct callout_rtn  *deferred;
        const struct armv_pte     *pte;
        const struct armv_pte     *pte_wa;
        const struct armv_pte     *pte_wb;
        const struct armv_pte     *pte_wt;
        void                      (*setup)(struct cpuinfo_entry *cpu, unsigned cpuid);
        const struct armv_chip    *(*detect)(void);
        unsigned short            ttb_attr;
        unsigned short            pte_attr;
};

Description:

The armv_chip structure describes the configuration for a particular CPU.

Note:

The ARMv7 processors use the WFI instruction to enter “wait for interrupt” mode.

To enable swap instructions, bit 10 (ARM_MMU_CR_F) must be set. In ARMv7, it's disabled by default, causing it to generate illegal instruction exceptions.

The members of the armv_chip structure include:

cpuid
Contains bits 15:0 of the CP15 main ID register.

The armv_list[] array defined in armv_list.c contains a list of all supported CPUs, and the arm_chip_detect() function iterates through this array to match bits 15:0 of the ID register.

A BSP can override the library's armv_list.c to provide a customized list of supported CPUs, for example to specify armv_chip structures that aren't implemented in libstartup, or to restrict the list to the processor(s) implemented by the target board.

name
The textual name of the processor.
mmu_cr_set
Specifies which bits to set in the MMU control register when the MMU is enabled in vstart().
mmu_cr_clr
Specifies which bits to clear in the MMU control register when the MMU is enabled in vstart().
cycles
The number of CPU cycles taken by the arm_cpuspeed.c calibration loop (which calculates loop cycles based on processor architecture from the ID register).
cache
A pointer to an armv_cache structure describing the cache configuration.
power
A pointer to the CPU-specific power kernel callout.

If no power kernel callout is specified, the kernel's idle loop simply busy-loops, and the sysmgr_cpumode() call fails with ENOSYS.

flush and deferred
Pointers to the CPU-specific kernel callouts used by procnto to handle unmapping pages.

The flush callout is used to flush the cache and TLB when unmapping a page. This is called for each page in a region being unmapped.

The deferred callout is used after all pages in a region have been unmapped, and can be used to perform any actions that the flush callout didn't perform.

For example, if the MMU doesn't support flushing the instruction cache by virtual address, the deferred callout can be used to flush the instruction cache after all pages have been unmapped, to reduce the cost of flushing.

pte
A pointer to the default page table configuration
pte_wa
A pointer to the page table configuration for write-allocate cache behavior.

If you specify the -wa option, the pte_wa configuration is used. If the CPU doesn't support write-allocate caching, set pte_wa to 0, and the default pte values will be used instead.

pte_wb
A pointer to the page table configuration for write-back cache behavior.

If you specify the -wb compile option, the pte_wb configuration is used. If the CPU doesn't support write-back caching, set pte_wb to 0, and the default pte values will be used instead.

Note: The pte_wb member isn't supported by MPCore.
pte_wt
A pointer to the page table configuration for write-through cache behavior.

If you specify the -wt compile option, the pte_wt configuration is used. If the CPU doesn't support write-through caching, set pte_wt to 0, and the default pte values will be used instead.

Note: The pte_wt member isn't supported by MPCore.
setup
A pointer to a function that performs additional CPU-specific initialization.
detect
A pointer to a function that checks for various configurations for Cortex A-8 and Cortex A-9 processors.
ttb_attr
Cacheability attributes for hardware page table walks.
pte_attr
Cacheability attributes for page table mappings used by the memory manager to manipulate L1/L2 page table entries.

Returns:

>0
Success.
-1
Error