_pci_cardbus_config

PCI card bus configuration registers

Synopsis:

#include <qvm/hw_pci.h>

struct _pci_cardbus_config_regs {
    uint16_t Vendor_ID;
    uint16_t Device_ID;
    uint16_t Command;
    uint16_t Status;
    uint8_t Revision_ID;
    uint8_t Class_Code[3];
    uint8_t Cache_Line_Size;
    uint8_t Latency_Timer;
    uint8_t Header_Type;
    uint8_t BIST;
    uint32_t Socket_Exca_Base_Reg;
    uint8_t Capabilities_Pointer;
    uint8_t reserved1;
    uint16_t Secondary_Status;
    uint8_t Pci_Bus_Num;
    uint8_t Cardbus_Bus_Num;
    uint8_t Sub_Bus_Num;
    uint8_t Cardbus_Latency_Timer;
    uint32_t Mem_Base_Reg_0;
    uint32_t Mem_Limit_Reg_0;
    uint32_t Mem_Base_Reg_1;
    uint32_t Mem_Limit_Reg_1;
    uint32_t Io_Base_Reg_0;
    uint32_t Io_Limit_Reg_0;
    uint32_t Io_Base_Reg_1;
    uint32_t Io_Limit_Reg_1;
    uint8_t Interrupt_Line;
    uint8_t Interrupt_Pin;
    uint16_t Bridge_Control;
    uint16_t Subsystem_Vendor_Id;
    uint16_t Subsystem_Id;
    uint32_t If_Legacy_Base_Reg;
    uint8_t reserved2[56];
    uint32_t System_Control;
    uint8_t reserved3[8];
    uint32_t Multifunction_Routing;
    uint8_t Retry_Status;
    uint8_t Card_Control;
    uint8_t Device_Control;
    uint8_t Buffer_Control;
    uint32_t Dma_Reg_0;
    uint32_t Dma_Reg_1;
    uint8_t Device_Dependent_Regs[100];
} ;

Data:

uint16_t Vendor_ID: 0x00
uint16_t Device_ID: 0x02
uint16_t Command: 0x04
uint16_t Status: 0x06
uint8_t Revision_ID: 0x08
uint8_t Class_Code[3]: 0x09
uint8_t Cache_Line_Size: 0x0C
uint8_t Latency_Timer: 0x0D
uint8_t Header_Type: 0x0E
uint8_t BIST: 0x0F
uint32_t Socket_Exca_Base_Reg: 0x10
uint8_t Capabilities_Pointer: 0x14
uint8_t reserved1: 0x15
uint16_t Secondary_Status: 0x16
uint8_t Pci_Bus_Num: 0x18
uint8_t Cardbus_Bus_Num: 0x19
uint8_t Sub_Bus_Num: 0x1A
uint8_t Cardbus_Latency_Timer: 0x1B
uint32_t Mem_Base_Reg_0: 0x1C
uint32_t Mem_Limit_Reg_0: 0x20
uint32_t Mem_Base_Reg_1: 0x24
uint32_t Mem_Limit_Reg_1: 0x28
uint32_t Io_Base_Reg_0: 0x2C
uint32_t Io_Limit_Reg_0: 0x30
uint32_t Io_Base_Reg_1: 0x34
uint32_t Io_Limit_Reg_1: 0x38
uint8_t Interrupt_Line: 0x3C
uint8_t Interrupt_Pin: 0x3D
uint16_t Bridge_Control: 0x3E
uint16_t Subsystem_Vendor_Id: 0x40
uint16_t Subsystem_Id: 0x42
uint32_t If_Legacy_Base_Reg: 0x44
uint8_t reserved2[56]: 0x48
uint32_t System_Control: 0x80
uint8_t reserved3[8]: 0x84
uint32_t Multifunction_Routing: 0x8C
uint8_t Retry_Status: 0x90
uint8_t Card_Control: 0x91
uint8_t Device_Control: 0x92
uint8_t Buffer_Control: 0x93
uint32_t Dma_Reg_0: 0x94
uint32_t Dma_Reg_1: 0x98
uint8_t Device_Dependent_Regs[100]: Device-dependent registers

Library:

Provided by qvm; no external library is required.

Description:

See the PCI specification.