_pci_bridge_config

PCI bridge configuration registers

Synopsis:

#include <qvm/hw_pci.h>

struct _pci_bridge_config_regs {
    uint16_t Vendor_ID;
    uint16_t Device_ID;
    uint16_t Command;
    uint16_t Status;
    uint8_t Revision_ID;
    uint8_t Class_Code[3];
    uint8_t Cache_Line_Size;
    uint8_t Latency_Timer;
    uint8_t Header_Type;
    uint8_t BIST;
    uint32_t Base_Address_Regs[2];
    uint8_t Primary_Bus_Number;
    uint8_t Secondary_Bus_Number;
    uint8_t Subordinate_Bus_Number;
    uint8_t Secondary_Latency_Timer;
    uint8_t IO_Base;
    uint8_t IO_Limit;
    uint16_t Secondary_Status;
    uint16_t Memory_Base;
    uint16_t Memory_Limit;
    uint16_t Prefetchable_Memory_Base;
    uint16_t Prefetchable_Memory_Limit;
    uint32_t Prefetchable_Base_Upper32;
    uint32_t Prefetchable_Limit_Upper32;
    uint16_t IO_Base_Upper16;
    uint16_t IO_Limit_Upper16;
    uint8_t Capabilities_Pointer;
    uint8_t Reserved1[3];
    uint32_t ROM_Base_Address;
    uint8_t Interrupt_Line;
    uint8_t Interrupt_Pin;
    uint16_t Bridge_Control;
    uint8_t Device_Dependent_Regs[192];
} ;

Data:

uint16_t Vendor_ID: 0x00
uint16_t Device_ID: 0x02
uint16_t Command: 0x04
uint16_t Status: 0x06
uint8_t Revision_ID: 0x08
uint8_t Class_Code[3]: 0x09
uint8_t Cache_Line_Size: 0x0C
uint8_t Latency_Timer: 0x0D
uint8_t Header_Type: 0x0E
uint8_t BIST: 0x0F
uint32_t Base_Address_Regs[2]: 0x10
uint8_t Primary_Bus_Number: 0x18
uint8_t Secondary_Bus_Number: 0x19
uint8_t Subordinate_Bus_Number: 0x1A
uint8_t Secondary_Latency_Timer: 0x1B
uint8_t IO_Base: 0x1C
uint8_t IO_Limit: 0x1D
uint16_t Secondary_Status: 0x1E
uint16_t Memory_Base: 0x20
uint16_t Memory_Limit: 0x22
uint16_t Prefetchable_Memory_Base: 0x24
uint16_t Prefetchable_Memory_Limit: 0x26
uint32_t Prefetchable_Base_Upper32: 0x28
uint32_t Prefetchable_Limit_Upper32: 0x2c
uint16_t IO_Base_Upper16: 0x30
uint16_t IO_Limit_Upper16: 0x32
uint8_t Capabilities_Pointer: 0x34
uint8_t Reserved1[3]: 0x35
uint32_t ROM_Base_Address: 0x38
uint8_t Interrupt_Line: 0x3C
uint8_t Interrupt_Pin: 0x3D
uint16_t Bridge_Control: 0x3E
uint8_t Device_Dependent_Regs[192]: Device-dependent registers

Library:

Provided by qvm; no external library is required.

Description:

See the PCI specification.