This structure contains the ARM-specific information:
- L1_vaddr
- Virtual address of the MMU level 1 page table used to map the kernel.
- L1_paddr
- Physical address of the MMU level 1 page table used to map the kernel.
- startup_base
- Virtual address of a 1-1 virtual-physical mapping used
to map the startup code that enables the MMU. This virtual
mapping is removed when the kernel is initialized.
- startup_size
- Size of the mapping used for startup_base.
- cpu
- Structure containing ARM core-specific operations and
data. Currently this contains the following:
- page_flush
- A routine used to implement CPU-specific cache/TLB
flushing when the memory manager unmaps or changes the
access protections to a virtual memory mapping for a page.
This routine is called for each page in a range being
modified by the virtual memory manager.
- page_flush_deferred
- A routine used to perform any operations that can be
deferred when page_flush is called. For
example on the SA-1110 processor, an Icache flush
is deferred until all pages being operated on have been
modified.