Give special attributes to a shared memory object
#include <sys/mman.h> int shm_ctl_special( int fd, int flags, uint64_t paddr, uint64_t size, unsigned special );
If you create anonymous shared memory objects (by calling mmap() with MAP_ANON | MAP_SHARED and a file descriptor of -1), a MAP_LAZY flag implicitly sets the SHMCTL_LAZY flag on the object.
|Some of the above bits have specific meanings for different processors. For more information, see the documentation for shm_ctl().|
Use the -l c option to qcc to link against this library. This library is usually included automatically.
The shm_ctl_special() function modifies the attributes of the shared memory object identified by the handle, fd. This handle is the value returned by shm_open().
The shm_ctl_special() function is similar to shm_ctl(), but has an additional processor-specific argument, special.
For ARM platforms, the special argument specifies the page table entry (PTE) bits to be set when the object is mapped. These bits and their meaning are generally processor-specific:
For ARMv4 processors (e.g. ARM926-based SoCs), you can specify the following:
For ARMv5 processors using extended small pages (e.g. xscale-based SoCs), you can specify the following:
For ARMv6 processors (e.g. ARM11-based SoCs), you can specify the following:
These special PPC flags refer to the bits in the page table entries that map the object:
|Flag||Definition||If the bit is 0:||If the bit is 1:|
(endian-ness, which is available only on some chips)
|Refers to the bit ordering used to represent data.||The page is accessed in big-endian byte order.||Not accessed in big-endian byte order.|
|Prevents speculative, out of sequence accesses from being performed on a region (i.e. instruction prefetches for speculative accesses).||Access to the page isn't guarded and can be done before it's known if required by sequential execution.||All loads and stores to the page are performed without speculation (they are known to be required).|
|Marks the page as uncacheable, meaning that the cache is always bypassed, and that all loads and stores access main memory.||The page is cacheable.||The page is cache-inhibited, and the data should not be cached downstream from the processor.|
(memory coherence required)
|Refers to system memory coherence.||The transaction is ignored, meaning that memory is not coherent or that this is a transaction that doesn't need to be looked at; memory coherence is not required.||Memory coherence is required.|
(write through cache)
|Operations update the main memory as well as the cache.||The page is a write-back (for coherency) in the system, and the data must be forwarded at least one cache level toward memory.||All stores performed to this page are written to main memory, meaning that the data for a write transaction is forwarded to system memory, or to a memory-mapped device.|
For additional information about these bits, see a PPC architecture guide.
On SH4 7760, the special argument controls the space attribute bits of the UTLB (see section 6.3.1 of 7760 hardware manual).
mmap(), munmap(), mprotect(), shm_ctl(), shm_open(), shm_unlink(), ThreadCtl()