Maintain, update, and regenerate groups of programs (POSIX)
make [options] [macro=name] [target]
QNX Neutrino, Linux, Microsoft Windows
If there are multiple instances of this option, they're processed in the order specified.
The make utility is used to maintain current versions of files by resolving time dependencies. If the file that make is examining (i.e. the target) is older than the file(s) on which it depends (i.e. the prerequisites), then make executes a list of shell commands associated with the target to create or update the target.
To control what make does, the utility refers to specifications (rules) consisting of a target, prerequisites, and a list of shell commands to be executed when a prerequisite is newer than the target. To simplify maintenance of programs, make has a collection of default macros and inference rules allowing it to identify the proper procedures required to update targets based on minimal information. (If the -r option is given, the builtin rules aren't used.)
For example, to compile myprog.c and produce the executable program myprog:
This works even in the absence of a makefile. The alternative of using the qcc utility produces an executable named a.out by default. Using make for compiling single-source executables is a convenient shortcut.
|When cross compiling, you can't rely on the default rules; you need to specify the target.|
The make utility attempts to perform the actions required to ensure that the specified target(s) are up-to-date. A target is considered out-of-date if it's older than any of its prerequisites. The make utility treats all prerequisites as targets themselves and recursively ensures that they're up-to-date. The utility examines the modified times of files to determine whether they're out-of-date.
After all the prerequisites of a target are ensured to be up-to-date, and if the target is out-of-date, the shell commands associated with the target entry are executed. If no shell commands are listed for the target, it's treated as up-to-date.
For more information on make and writing makefiles, see the GNU website at http://www.gnu.org/.
Typing this in the absence of a makefile (or with a makefile that doesn't mention the myfile.o file) uses the builtin suffixes list and inference rules to determine the name of the source file and, if necessary, to run the proper command to create or rebuild the myfile.o file.
Suppose you have the source files myfile1.c, myfile2.c, and myfile3.c. The first two files include the headers <hdr1.h> and <hdr2.h>, and these files are all linked together to produce the program myprog. Here's what a simple makefile describing this could look like:
# Samplemakefile1 myprog: myfile1.o myfile2.o myfile3.o myfile1.o: hdr1.h hdr2.h myfile2.o: hdr1.h hdr2.h myfile3.o:
To compile and link myprog:
Or since myprog is the first target:
To see what commands need to be executed without actually executing them:
Using macros, the myprog makefile could be simplified to:
# Samplemakefile2 OBJS=myfile1.o myfile2.o myfile3.o HDRS=hdr1.h hdr2.h myprog: $(OBJS) myfile1.o: $(HDRS) myfile2.o: $(HDRS)
This makefile is functionally identical to the previous example. It isn't significantly better, just slightly more generalized.
We can further simplify the makefile by using the builtin inference rules and macros, as follows:
# Samplemakefile3 OBJS=myfile1.o myfile2.o myfile3.o HDRS=hdr1.h hdr2.h myprog: $(OBJS) myfile1.o myfile2.o: $(HDRS)
As you can see, this makefile is short and to-the-point. Again, this is functionally equivalent to the previous examples.
Using this makefile, you can customize the compilation from the make command line by setting the appropriate macros:
which defines the symbol HITHERE.
You can also direct the linker to produce a linkmap:
Of course, any of these macro assignments could be “hard-coded” in the makefile, but it's often convenient to override the defaults from the command line for special needs.
After make has started and the MAKEFLAGS variable has been read, all of the options except -d, -f, and -p are added to the MAKEFLAGS macro. The MAKEFLAGS macro is passed into the environment as an environment variable for all child processes.
When the -q option has been specified:
When the -q option hasn't been specified:
In makefiles, specify Windows pathnames using one of the following methods:
Conventions for Recursive Makefiles and Directories appendix of the QNX Neutrino Programmer's Guide
Andrew Oram and Steve Talbott, Managing Projects with make, O'Reilly and Associates, 1991